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8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 1 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer g eneral d escription the ics8430-111 is a general purpose, dual out- put high frequency synthesizer and a member of the hipercloc ks? f amily of high performance clock solutions from ics. the clk, nclk pair can accept most standard differential input lev- els. the single ended test_clk input accepts lvcmos or lvttl input levels and translates them to 3.3v lvpecl levels. the vco operates at a frequency range of 200mhz to 700mhz. with the output configured to divide the vco frequency by 2, output frequency steps as small as 2mhz can be achieved using a 16mhz differential or single ended reference clock. out- put frequencies up to 700mhz can be programmed using the serial or parallel interfaces to the configuration logic. the low jitter and frequency range of the ics8430-111 makes it an ideal clock generator for most clock tree applications. b lock d iagram p in a ssignment f eatures ? dual differential 3.3v lvpecl output ? selectable 14mhz to 27mhz differential clk, nclk or test_clk input ? clk, nclk accepts any differential input signal: lvpecl, lvhstl, lvds, sstl, hcsl ? test_clk accepts the following input types: lvcmos, lvttl ? output frequency range up to 700mhz ? vco range: 200mhz to 700mhz ? parallel or serial interface for programming counter and output dividers ? cycle-to-cycle jitter: 25ps (maximum) ? 3.3v supply voltage ? 0c to 70c ambient operating temperature ? industrial termperature information available upon request vco_sel clk_sel test_clk clk s_load s_data s_clock np_load m0:m8 n0:n2 vco pll fout0 nfout0 fout1 nfout1 test n configuration interface logic m 0 1 0 1 16 phase detector 2 hiperclocks? ics nclk mr the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice. 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 clk test_clk clk_sel v cca s_load s_data s_clock mr m5 m6 m7 m8 n0 n1 n2 v ee v ee nfout0 fout0 v cco nfout1 fout1 v cc test nclk np_load vco_sel m0 m1 m2 m3 m4 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view ics8430-111
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 2 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer the parallel input mode. the relationship between the vco fre- quency, the input frequency and the m divider is defined as follows: the m value and the required values of m0 through m8 are shown in table 3b, programmable vco frequency function table. valid m values for which the pll will achieve lock for a 16mhz reference are defined as 100 m 350. the frequency out is defined as follows: serial operation occurs when np_load is high and s_load is low. the shift register is loaded by sampling the s_data bits with the rising edge of s_clock. the contents of the shift register are loaded into the m divider and n output divider when s_load transitions from low-to-high. the m divide and n output divide values are latched on the high-to-low transition of s_load. if s_load is held high, data at the s_data input is passed directly to the m divider and n output divider on each rising edge of s_clock. the serial mode can be used to program the m and n bits and test bits t1 and t0. the internal registers t0 and t1 determine the state of the time s erial l oading p arallel l oading t s t h t s t h t s m, n f unctional d escription the ics8430-111 features a fully integrated pll and there- fore requires no external components for setting the loop bandwidth. a differential clock input is used as the input to the on-chip oscillator. the output of the oscillator is divided by 16 prior to the phase detector. a16mhz clock input provides a 1mhz reference frequency. the vco of the pll operates over a range of 200 to 700mhz. the output of the m divider is also applied to the phase detector. the phase detector and the m divider force the vco output frequency to be 2m times the reference frequency by adjust- ing the vco control voltage. note that for some values of m (either too high or too low), the pll will not achieve lock. the output of the vco is scaled by a divider prior to being sent to each of the lvpecl output buffers. the divider provides a 50% output duty cycle. the programmable features of the ics8430-111 support two input modes to program the m divider and n output divider. the two input operational modes are parallel and serial. fig- ure 1 shows the timing diagram for each mode. in parallel mode the np_load input is initially low. the data on inputs m0 through m8 and n0 through n2 is passed directly to the m divider and n output divider. on the low-to-high transition of the np_load input, the data is latched and the m divider remains loaded until the next low transition on np_load or until a serial event occurs. as a result, the m and n bits can be hardwired to set the m divider and n output divider to a specific default state that will automatically occur during power-up. the test output is low when operating in fvco = f in x m t1 t0 test output 0 0 low 0 1 s_data, shift register input 1 0 output of m divider 1 1 cmos fout f igure 1. p arallel & s erial l oad o perations * note: the null timing slot must be observed. s_clock s_data s_load np_load m0:m8, n0:n1 np_load s_load fout = fvco = f in x m nn
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 3 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d , 3 , 2 , 1 0 3 , 9 2 , 8 2 2 3 , 1 3 , 7 m , 6 m , 5 m , 2 m , 1 m , 0 m 4 m , 3 m t u p n in w o d l l u p n o i t i s n a r t h g i h - o t - w o l n o d e h c t a l a t a d . s t u p n i r e d i v i d m . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i d a o l _ p n f o 48 mt u p n ip u l l u p 6 , 51 n , 0 nt u p n in w o d l l u p c 3 e l b a t n i d e n i f e d s a e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e l b a t n o i t c n u f 72 nt u p n ip u l l u p 6 1 , 8v e e r e w o p. s n i p y l p p u s e v i t a g e n 9t s e tt u p t u o . n o i t a r e p o f o e d o m l a i r e s e h t n i e v i t c a s i h c i h w t u p t u o t s e t . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e d o m l e l l a r a p n i w o l n e v i r d t u p t u o 0 1v c c r e w o p. n i p y l p p u s e r o c 2 1 , 1 1 , 1 t u o f 1 t u o f n t u p t u o . s l e v e l e c a f r e t n i l c e p v l v 3 . 3 . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d 3 1v o c c r e w o p. n i p y l p p u s t u p t u o 5 1 , 4 1 , 0 t u o f 0 t u o f n t u p t u o . s l e v e l e c a f r e t n i l c e p v l v 3 . 3 . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d 7 1r mt u p n in w o d l l u p s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a d e t r e v n i e h t d n a w o l o g o t x t u o f s t u p t u o e u r t e h t g n i s u a c t e s e r e r a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t x t u o f n s t u p t u o d e d a o l t c e f f a t o n s e o d r m f o n o i t r e s s a . d e l b a n e e r a s t u p t u o e h t d n a . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s e u l a v t d n a , n , m 8 1k c o l c _ st u p n in w o d l l u p r e t s i g e r t f i h s e h t o t n i t u p n i a t a d _ s t a t n e s e r p a t a d l a i r e s n i s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s f o e g d e g n i s i r e h t n o 9 1a t a d _ st u p n in w o d l l u p f o e g d e g n i s i r e h t n o d e l p m a s a t a d . t u p n i l a i r e s r e t s i g e r t f i h s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s 0 2d a o l _ st u p n in w o d l l u p . s r e d i v i d e h t o t n i r e t s i g e r t f i h s m o r f a t a d f o n o i t i s n a r t s l o r t n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 2v a c c r e w o p. n i p y l p p u s g o l a n a 2 2 l e s _ k l c t u p n ip u l l u p e c n e r e f e r l l p e h t s a s t u p n i t s e t r o k c o l c l a i t n e r e f f i d n e e w t e b s t c e l e s k l c _ t s e t s t c e l e s . h g i h n e h w s t u p n i k l c n , k l c s t c e l e s . e c r u o s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . w o l n e h w 3 2k l c _ t s e tt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c t s e t 4 2k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 5 2k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 6 2d a o l _ p nt u p n in w o d l l u p s i 0 m : 8 m t a t n e s e r p a t a d n e h w s e n i m r e t e d . t u p n i d a o l l e l l a r a p s t e s 0 n : 2 n t a t n e s e r p a t a d n e h w d n a , r e d i v i d m e h t o t n i d e d a o l . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e u l a v r e d i v i d t u p t u o n e h t 7 2l e s _ o c vt u p n ip u l l u p . e d o m s s a p y b r o l l p n i s i r e z i s e h t n y s r e h t e h w s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 4 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 3b. p rogrammable vco f requency f unction t able (note 1) t able 3a. p arallel and s erial m ode f unction t able t able 3c. p rogrammable o utput d ivider f unction t able t u p n i e u l a v r e d i v i d n ) z h m ( y c n e u q e r f t u p t u o 2 n1 n0 nm u m i n i mm u m i x a m 000 2 0 0 10 5 3 00 1 4 0 55 7 1 010 8 5 25 . 7 8 011 6 15 . 2 15 7 . 3 4 10 0 1 0 0 20 0 7 10 1 2 0 0 10 5 3 110 4 0 55 7 1 111 8 5 25 . 7 8 s t u p n i s n o i t i d n o c r md a o l _ p nmnd a o l _ sk c o l c _ sa t a d _ s hx xxx x x . w o l s t u p t u o s e c r o f . t e s e r ll a t a da t a dx x x m e h t o t y l t c e r i d d e s s a p s t u p n i n d n a m n o a t a d . w o l d e c r o f t u p t u o t s e t . r e d i v i d t u p t u o n d n a r e d i v i d l a t a da t a dl x x d e d a o l s n i a m e r d n a s r e t s i g e r t u p n i o t n i d e h c t a l s i a t a d . s r u c c o t n e v e l a i r e s a l i t n u r o n o i t i s n a r t w o l t x e n l i t n u lh xxl a t a d n o a t a d h t i w d e d a o l s i r e t s i g e r t f i h s . e d o m t u p n i l a i r e s . k c o l c _ s f o e g d e g n i s i r h c a e n o a t a d _ s lh xx la t a d e h t o t d e s s a p e r a r e t s i g e r t f i h s e h t f o s t n e t n o c . r e d i v i d t u p t u o n d n a r e d i v i d m lh xx la t a d. d e h c t a l e r a s e u l a v r e d i v i d t u p t u o n d n a r e d i v i d m lh xxl x x . s r e t s i g e r t f i h s t c e f f a t o n o d t u p n i l a i r e s r o l e l l a r a p lh xxh a t a d. d e k c o l c s i t i s a r e d i v i d m o t y l t c e r i d d e s s a p a t a d _ s w o l = l : e t o n h g i h = h e r a c t ' n o d = x n o i t i s n a r t e g d e g n i s i r = n o i t i s n a r t e g d e g n i l l a f = y c n e u q e r f o c v ) z h m ( e d i v i d m 6 5 28 2 14 62 36 18421 8 m7 m6 m5 m4 m3 m2 m1 m0 m 0 0 20 0 1 001100100 2 0 21 0 1 001100101 4 0 22 0 1 001100110 6 0 23 0 1 001100111 ? ? ????????? ? ? ????????? 6 9 68 4 3 10 10 11100 8 9 69 4 3 101011101 0 0 70 5 3 10 10 11110 . z h m 6 1 f o y c n e u q e r f t u p n i n a o t d n o p s e r r o c s e i c n e u q e r f g n i t l u s e r e h t d n a s e u l a v e d i v i d m e s e h t : 1 e t o n
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 5 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 4a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c y l p p u s e r o c5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v g o l a n a5 3 1 . 33 . 35 6 4 . 3v v o c c e g a t l o v t u p u o5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 0 2 1a m i a c c t n e r r u c y l p p u s g o l a n a 0 1a m t able 4b. lvcmos/lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h , r m , 1 n , 0 n , 7 m - 0 m , d a o l _ s , a t a d _ s , k c o l c _ s d a o l _ p n , k l c _ t s e t v c c v = n i v 5 6 4 . 3 =0 5 1a l e s _ o c v , l e s _ k l c , 2 n , 8 mv c c v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l , r m , 1 n , 0 n , 7 m - 0 m , d a o l _ s , a t a d _ s , k c o l c _ s d a o l _ p n , k l c _ t s e t v c c , v 5 6 4 . 3 = v n i v 0 = 5 -a l e s _ o c v , l e s _ k l c , 2 n , 8 m v c c v 5 6 4 . 3 =, v n i v 0 = 0 5 1 -a v h o t u p t u o e g a t l o v h g i h 1 e t o n ; t s e t6 . 2v v l o t u p t u o e g a t l o v w o l 1 e t o n ; t s e t 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c . 2 / a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, v o -0.5v to v cco + 0.5v package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 6 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 5. i nput f requency c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c t able 4d. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c e h t n i e r u g i f t i u c r i c t s e t d a o l t u p t u o v 3 . 3 e e s . v 2 - . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i y c n e u q e r f t u p n i 1 e t o n ; k l c _ t s e t4 17 2z h m 1 e t o n ; k l c n , k l c4 17 2z h m k c o l c _ s 0 5z h m n i h t i w e t a r e p o o t o c v e h t r o f t e s e b t s u m e u l a v m e h t , e g n a r y c n e u q e r f e c n e r e f e r d n a t u p n i l a i t n e r e f f i d e h t r o f : 1 e t o n 5 1 1 e r a m f o s e u l a v d i l a v , z h m 4 1 f o y c n e u q e r f t u p n i m u m i n i m e h t g n i s u . e g n a r z h m 0 0 7 o t z h m 0 0 2 e h t m . 0 0 4 0 6 e r a m f o s e u l a v d i l a v , z h m 7 2 f o y c n e u q e r f m u m i x a m e h t g n i s u m . 8 0 2 l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c nv n i v = c c v 5 6 4 . 3 =5a k l cv n i v = c c v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i k l c nv n i v , v 0 = c c v 5 6 4 . 3 =0 5 1 -a k l cv n i v , v 0 = c c v 5 6 4 . 3 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n v e e 5 . 0 +v c c 5 8 . 0 -v s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n , v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t c c . v 3 . 0 + s i e g a t l o v e d o m n o m m o c : 2 e t o nv s a d e n i f e d h i . t able 4c. d ifferential dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 7 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 6. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 7z h m t ) c c ( t i j1 e t o n ; r e t t i j e l c y c - o t - e l c y c z h m 5 . 7 8 > t u o f5 2s p z h m 5 . 7 8 < t u o f0 4s p t ) r e p ( t i js m r , r e t t i j d o i r e p 5 . 9s p t ) o ( k s2 , 1 e t o n ; w e k s t u p t u o 5 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p t s e m i t p u t e s d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n t h e m i t d l o h d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n c d oe l c y c y t u d t u p t u o n 18 42 5% 1 = n5 45 5% t k c o l e m i t k c o l l l p 1s m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 8 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer p arameter m easurement i nformation o utput r ise /f all t ime c ycle - to -c ycle j itter p eriod j itter d ifferential i nput l evel o utput s kew 3.3v o utput l oad ac t est c ircuit o utput d uty c ycle /p ulse w idth /p eriod scope qx nqx lvpecl v cc , v cca , v cco = 2v v ee = -1.3v 0.165v v cmr cross points v pp v cc v ee clk nclk t sk(o) nfoutx foutx nfouty fouty clock outputs 20% 80% 80% 20% t r t f v sw i n g t pw t period t pw t period odc = x 100% foutx nfoutx ? ? ? ? t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 foutx nfoutx v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 9 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics8430-111 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. p ower s upply f iltering t echniques f igure 2. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminat- ing resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination v cc - 2v drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. there are a few simple termination schemes. figures 3a and 3b show two different layouts which are recom- mended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 10 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer figure 4 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 4. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 11 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer f igure 5c. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 5b. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 5d. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 5a to 5e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 5a. h i p er c lock s clk/ n clk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 5a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 5e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 12 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics8430-111. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8430-111 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 120ma = 415.8mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power _max (3.465v, with all outputs switching) = 415.8mw + 60mw = 475.8mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.476w * 42.1c/w = 90c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67. 8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47. 9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 7. t hermal r esistance ja for 32- pin lqfp, f orced c onvection
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 13 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ) * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ) * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 14 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer r eliability i nformation t ransistor c ount the transistor count for ics8430-111 is: 3960 t able 8. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 15 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer p ackage o utline - y s uffix for 32 l ead lqfp t able 9. p ackage d imensions n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 6 . 1 1 a 5 0 . 05 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 00 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 q 0 7 c c c 0 1 . 0 reference document: jedec publication 95, ms-026
8430dy-111 www.icst.com/products/hiperclocks.html rev. f june 1, 2005 16 preliminary integrated circuit systems, inc. ics8430-111 700mh z , l ow j itter d ifferential - to -3.3v lvpecl f requency s ynthesizer t able 10. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring e xtended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 1 1 - y d 0 3 4 8 s c i1 1 1 - y d 0 3 4 8 s c ip f q l d a e l 2 3y a r tc 0 7 o t c 0 t 1 1 1 - y d 0 3 4 8 s c i1 1 1 - y d 0 3 4 8 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 0 7 o t c 0 the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the unite d states and/or other countries.

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